The present invention relates to a method of and an apparatus for displaying a plurality of screen modes wherein image data can be displayed in any one of the screen modes having image display regions different from each other.
In this type of information processing apparatus for displaying images, image data is first temporarily stored in a video memory and the image data read from the video memory is then displayed on a cathode-ray tube (CRT). In this case, the storage capacity of the video memory is relatively small and the data reading speed is also low. Therefore, the image data are displayed on the CRT in a low-resolution screen mode.
While, the video memory has been brought to large storage capacity with the recent rapid advancement in technique and the data reading speed has been highly increased. Thus, there is now an increasing tendency that the image data can be displayed in high resolution.
Further, there has been proposed a multi-scan CRT capable of displaying the image data in the low-resolution screen mode and image data in a high-resolution screen mode.
When image data represented in a format of 640.times.400 pixels, for example, is displayed on the multi-scan CRT in the low-resolution mode, the following control is executed.
That is, a control program is first executed so that mode information for a horizontal synchronizing frequency of 24 KHz is set to a mode register. Then, a multiplexer changes or sets a pixel clock for reading the pixel data stored in the video memory based on the set 24 KHz mode information to 21 MHz, for example. Further, the control program is executed so as to set synchronizing width information, synchronizing periodic or cyclic information, display start-position information and display completion- or end-position information for a low-resolution screen mode.
A synchronizing signal generator generates a synchronizing signal having a horizontal synchronizing frequency of 24 KHz and a vertical synchronizing frequency of 55 Hz, for example, based on the pixel clock and both the synchronizing width information and the synchronizing cyclic information for the low-resolution screen mode.
Next, a display timing generator generates a display timing signal based on the pixel clock, the synchronizing signal and both the display start-position information and the display end-position information for the low-resolution screen mode. In response to the synchronizing signal and the display timing signal, the multi-scan CRT displays image data in the low-resolution screen mode on a display region of the screen, which is represented in the form or format of 640.times.400 pixels.
When, on the other hand, the image data in 640.times.480 pixels is displayed on the multi-scan CRT in the high-resolution screen mode, the following control is executed.
A control program is first executed so as to set mode information for a horizontal synchronizing frequency of 31 KHz, for example, to the mode register. Then, the multiplexer switches or sets the pixel clock to 25 MHz, for example, based on the set 31 KHz mode information. Further, the control program is executed so as to set up synchronizing width information, synchronizing cyclic information, display start-position information and display end-position information for a high-resolution screen mode.
The synchronizing signal generator generates a synchronizing signal having a horizontal synchronizing frequency of 31 KHz and a vertical synchronizing frequency of 60 Hz, for example, based on the pixel clock and both the synchronizing width information and the synchronizing cyclic information for the high-resolution screen mode.
Next, the display timing generator produces a display timing signal based on the pixel clock, the synchronizing signal and both the display start-position information and the display end-position information for the high-resolution screen mode. In response to the synchronizing signal and the display timing signal, the multi-scan CRT displays, in the high-resolution screen mode, image data on a display region of the screen, which is represented in the format of 640.times.480 pixels.
According to the conventional apparatus, as has been described above, the two kinds of pixel clocks are generated to realize the low-resolution screen mode and the high-resolution screen mode. Further, the synchronizing signals and the display timing signals are separately produced in accordance with their corresponding pixel clocks. Therefore, the apparatus is rendered complex in structure and high in cost.